RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 70

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.2 Multiple Client Architecture
3.2.4 Peer-to-Peer Transfers
Figure 3-2. Peer-to-Peer vs. Centralized Memory Data Transfers
3-4
Frame I/O
Peer
PCI
PCI Card
Memory
Peer
The multiple queue architecture of the RS8234 also enables peer-to-peer PCI
transfers. The RS8234 transfers ATM cells as a PCI master. Since the buffer
control structures are independent for each peer, each identifies a unique address
range in PCI memory space. The host defines the address range of each peer. The
RS8234 transfers data within this address range. An address range corresponds
either to a region of centralized host memory, or to a set of peer resident buffers.
Figure 3-2
buffers require store-forward operations, while the peer buffers enable
peer-to-peer transfers. Thus, peer-to-peer transfers reduce the use of the PCI bus.
Frame I/O
Host
PCI
PCI Motherboard
Mindspeed Technologies
PCI BUS
shows the difference between these two options. Centralized memory
2
Centralized
1
Memory
ATM ServiceSAR Plus with xBR Traffic Management
1
LEGEND:
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RS8234
PCI Transaction
Peer-to-Peer Transaction
Centralized Memory Transaction
Data Buffer
28234-DSH-001-B
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RS8234
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