RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 253

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Figure 10-7. i960CA/CF to the RS8234 Interface
28234-DSH-001-B
NOTE(S):
(1)
Required for full 8 MB address range.
RS8234
LADDR[18:2]
PROCMODE
LDATA[31:0]
PBSEL[1:0]
RAMMODE
MWE[3:0]*
PADDR[0]
PADDR[1]
PBE[3:0]*
LADDR[1]
LADDR[0]
PBLAST*
SYSCLK
MCS[3]*
MCS[2]*
MCS[1]*
MCS[0]*
PDAEN*
PWAIT*
10.4 Processor Interface Signals
Figure 10-7
i960CA/CF processor. The memory region decoded for PCS* should be set for
N
one wait state SRAM), and N
enabled, and burst can be enabled or disabled at the system designer’s option.
Pulling up the i960 CLKMODE input to a logic one selects the divide-by-one
clock mode, making i960 PCLK synchronous to SYSCLK.
PFAIL*
PRDY*
PRST*
PWNR
MWR*
PINT*
MOE*
PAS*
RAD
PCS*
and N
Mindspeed Technologies
For by_16 SRAM
GND for by_8 or by_4,
VCC for by_16
GND
illustrates the signal interface between the RS8234 device and the
WAD
SRAMCS*
SRAMCS*
SRAMCS*
SRAMCS*
= 2, N
x17 Buff
x32 Xcvr
Decode
RDD
and N
(1)
XDA
= 1. In addition, external ready control must be
WDD
Pullup
NC
= 0 or 1 (depending on the use of zero or
™
OE
WE[3:0]
D[31:0]
A[18:2]
A[1]
A[0]
A[31:28]
CLKMODE
CLKIN
RESET*
XINT0
FAIL*
AS*
W/R*
WAIT*
BLAST*
READY*
BE[3:0]*
A[22:21]
A[2]
A[3]
D[31:0]
DT/R*
PCLK
A[20:4]
i960CA/CF
SRAM
10.0 Local Processor Interface
10.4 Processor Interface Signals
100074_076
10-11