RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 72

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.3 Write-Only Control and Status
3.3.1 Write-Only Control Queues
3-6
3.3 Write-Only Control and Status
For host-based applications, the host manages the RS8234 SAR using write-only
control and status queues. This architecture minimizes PCI bus utilization by
eliminating reads from the control path. PCI writes utilize the bus much more
efficiently than PCI reads. During a PCI write, the target may “post” the write
data in an internal FIFO, terminate the transaction, and immediately release the
bus. On the other hand, during reads, the target retrieves the data while holding
the bus. Since the data retrieval takes some time, reads increase the PCI bus
utilization.
(PDU) fetches. All control and status transactions are writes. This section
describes the management of write-only queues. The purpose and entries of each
class of queue are described in later chapters.
Table 3-1. RS8234 Control and Status Queues
The host controls run-time segmentation and reassembly through write-only
control queues. There are two types of control queues — the segmentation
transmit queues and the reassembly free buffer queues. The host submits buffers
of PDU data for segmentation on the transmit queues, and supplies empty buffers
for received data on the free buffer queues. Each type of queue is managed as a
write-only control queue.
register pointer. To allow multiple clients, the RS8234 supports 32 queues of each
type. The SAR and host manage each queue independently, through queue
management variables. The SAR stores its variables in internal registers called
base tables. The host maintains its own variables within its driver. Each queue
contains a programmable number of queue entries.
The RS8234’s write-only architecture uses reads only for segmentation data
Table 3-1
These queues reside in SAR shared memory at a location defined by a base
Control
Status
Type
Mindspeed Technologies
defines the RS8234 control and status queues.
Segmentation status queue
Transmit queue
Segmentation
ATM ServiceSAR Plus with xBR Traffic Management
™
Reassembly status queue
Free buffer queue
Reassembly
28234-DSH-001-B
RS8234