RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 65

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (5 of 6)
28234-DSH-001-B
PFAIL*
PINT*
PRST*
LDATA[31:0]
LADDR[18:2]
LADDR[1:0]
MCS[3:0]*
MOE*
MWE[3:0]*
MWR*
RAMMODE
CLK2X
SYSCLK
CLKD3
STAT[1:0]
Pin Label
Self-Test Failed
Interrupt Output
Reset Output
Memory Data Bus
Memory Address Bus
Memory Address Bus
Memory Bank Chip
Selects
Memory Read Enable
Memory Byte Write
Enables
Write Enable
RAM Mode Select
2x Clock Input
System Clock Output
Divide by 3 Clock
Output
SAR Status
Signal Name
Mindspeed Technologies
I/O
OD
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
The local processor can indicate a failure of its internal
self-test or initialization processes by asserting the PFAIL*
input to the RS8234.
Asserted by the RS8234 to the local processor to signal an
interrupt request in local processor mode.
Asserted by the RS8234 to the local processor whenever the
HRST* input is asserted, or when the LP_ENABLE bit in the
CONFIG0 register is a logic low.
Data I/O bus. Used for memory reads and writes, as well as
control and status register access by the local processor.
Address I/O bus. Used for memory reads and writes, as well
as control and status register access by the local processor.
The two least significant bits of address I/O bus. Used for
memory reads and writes, as well as control and status
register access by the local processor.
Selects one of four addressable banks of SRAM memory.
Indicates that a read cycle is proceeding and the memory
device output buffers should be enabled, driving data onto the
LDATA[31:0] lines.
Memory byte write enables for by_4 or by_8 SRAMs. For
by_16 devices, these outputs are byte enables that are active
on writes and reads.
Memory write enable for by_16 SRAMs.
Selects RAM chips supported.
1 = by_16 memory devices
0 = by_4 or by_8 memory devices
Double frequency (from SYSCLK) TTL clock input (66 MHz
maximum).
This divide by 2 of CLK2X is the internal system clock as well
as the external system clock (33MHz maximum).
This output clock is a 50% duty cycle, one-third divide of
CLK2X; it may be used for the UTOPIA interface clock (22 MHz
maximum).
RS8234 internal status outputs. Internal status controlled by
the STAT_MODE[4:0] field in the CONFIG0 Register.
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-33