RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 122

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.4 Buffer Management
5.4.1 Host vs. Local Reassembly
5-18
5.4 Buffer Management
Once CPCS-PDU processing has been implemented, the cell payloads are written
to data buffers. Each channel retrieves the location of its buffers from one of
32 free buffer queues. The reassembly coprocessor tracks the location of the
buffers from the VCC table entry for that channel.
NOTE:
Data buffers can reside in both host and SAR shared memory. The majority of
user data traffic should be reassembled in host memory. SAR shared memory
reassembly is intended for low bandwidth management and control functions,
such as OAM and Signaling. This allows an optional local processor to off-load
these network management functions from the host, focusing host processing
power on the user application.
Data buffers are supplied according to the mechanisms detailed below.
The process cycle time of a read transaction across the PCI bus is much
longer than a write transaction, due to the PCI bus being held in a busy
state while the remote processor accesses and processes the read request.
Therefore, to speed up processing flow during reassembly, the RS8234
uses only control and status writes across the PCI bus between host and
local systems.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234