RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 255

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 10-2. Standalone Interface Pins
28234-DSH-001-B
PROCMODE
PCS*
PBLAST*
PAS*
PWNR
PRDY*
PWAIT*
PDAEN*
PADDR[1:0]
PBSEL[1:0]
PBE[3:0]*
PFAIL*
NOTE(S):
(1)
(2)
Direction given with respect to the RS8234.
See the HOST_ISTAT0 Register for details.
Signal
Dir
O
O
O
O
O
I
I
I
I
I
I
I
(1)
10.6 Standalone Operation
Standalone interface pins and descriptions are given in
shows the signal interface between the RS8234 and the RS825x ATM
receiver/transmitter device with no local processor. The PCS*, PAS*, and PWNR
pins are now outputs providing chip select, address strobe, and write/read control
to the RS825x. PDAEN* is now an input connected to the interrupt sources of the
RS825x. PBLAST* is a second chip select, which can be used to connect a future
second Mindspeed PHY device. The PRDY* output is active and indicates the
cycles in which the data transaction occurs. The PWAIT* input is active and can
be used to prolong the cycle as shown in
other than the RS825x can be connected by using PWAIT* to extend the read or
write cycle, and by using external logic to translate the RS8234 control signals.
Processor interface mode select input. A logic one enables standalone operation without a
local processor.
Chip select output for PHY device number one. Synchronous to SYSCLK.
Chip select output for PHY device number two. Synchronous to SYSCLK.
PHY address strobe. Synchronous to SYSCLK.
PHY write/read select. A logic one on this output indicates a write cycle, a logic zero
indicates a read cycle. Synchronous to SYSCLK.
PHY interface ready signal. A logic low on this signal at rising edge of SYSCLK indicates
that the data cycle has been completed.
PHY wait input. Allows external logic to insert wait states to extend data cycles. Only
active when PRDY* is active.
PHY interrupt input, active low, level sensitive
Not used, pull to logic zero.
Not used, pull to logic zero.
Not used, pull to logic zero.
Not used, pull to logic one.
Mindspeed Technologies
Description
™
Figure
(2)
.
10-9. Physical interface devices
10.0 Local Processor Interface
Table
10.6 Standalone Operation
10-2.
Figure 10-8
10-13