RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 346

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

15.0 Electrical and Mechanical Specifications
15.1 Timing
15.1.3 System Clock Timing
The system clock timing consists of the CLK2X input and the SYSCLK and CLKD3 outputs. The CLK2X
input and SYSCLK outputs are used to generate the internal and external system clocks, as well as SAR shared
memory and processor read and write timing. The CLKD3 output can be used as the ATM physical interface
clock. There is no defined skew relationship between the CLK2X input and SYSCLK and CLKD3 outputs.
Table 15-4
timing.
Table 15-4. System Clock Timing
15-6
NOTE(S):
(1)
(2)
Symbol
See
See
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
dh
cd
sh
dr
cf
cr
cf
sf
sl
sr
sf
df
dl
df
d
c
s
Figure 15-5
Figure 15-6
specifies the timing parameters of the three clocks.
CLK2X Frequency
CLK2X Period
CLK2X Duty Cycle
CLK2X Rise Time
CLK2X Fall Time
SYSCLK Frequency
SYSCLK Period
SYSCLK High Time
SYSCLK Low Time
SYSCLK Rise Time
SYSCLK Fall Time
CLKD3 Frequency
CLKD3 Period
CLKD3 High Time
CLKD3 Low Time
CLKD3 Rise Time
CLKD3 Fall Time
for waveforms and definitions.
for waveforms and definitions. The outputs are measured with a load of 35 pF.
Parameter
Mindspeed Technologies
Output Clocks
Input Clocks
(1)
ATM ServiceSAR Plus with xBR Traffic Management
(2)
Figure 15-5
(t
(t
(t
(t
™
S
S
D
D
15.15
Min
/2) – 2
/2) – 2
/2) – 2
/2) – 2
40
0
0
0
1
1
1
1
and
Figure 15-6
t
t
CF
2t
CF
3t
/2
C
/3
C
(t
(t
(t
(t
S
S
D
D
Max
/2) + 2
/2) + 2
/2) + 2
/2) + 2
66
60
6
6
4
4
4
4
illustrates this
28234-DSH-001-B
Units
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
RS8234