R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1011

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC or DMAC. In a transmit operation, a TXI interrupt request is generated
when the TEND flag in SSR is set to 1. If the TXI interrupt request is designated beforehand as a
DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI interrupt
request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are
automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of
an error, the SCI retransmits the same data automatically. During this period, the TEND flag
remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or
DMAC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI interrupt request will be
generated in the event of an error, and the ERS flag will be cleared.
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI interrupt request is designated beforehand as a DTC or DMAC activation source, the
DTC or DMAC will be activated by the RXI interrupt request, and transfer of the receive data will
be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the
DTC or DMAC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the
DTC or DMAC is not activated, but instead, an ERI interrupt request is sent to the CPU.
Therefore, the error flag should be cleared.
When using the DTC or DMAC for transmission or reception, it is essential to set and enable the
DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting
procedures, refer to section 10, Data Transfer Controller (DTC), or section 8, DMA Controller
(DMAC).
REJ09B0565-0100 Rev. 1.00
Page 981 of 1448
Jul 22, 2010