R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1037

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
17.3.5
ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags
and status.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6
5
Bit Name
TDRE
TEND
RDRF
I
2
C Bus Status Register (ICSR)
Initial Value
0
0
0
R/W
R/W
R/W
R/W
Description
Transmit Data Register Empty
[Setting condition]
•
•
•
•
•
•
•
Transmit End
[Setting condition]
•
[Clearing conditions]
•
•
Receive Data Register Full
[Setting condition]
•
[Clearing conditions]
•
•
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty.
When TRS has been set.
When a start condition (including retransmission)
has been issued.
When a transition from the receive mode to the
transmit mode has been made in the slave mode.
[Clearing conditions]
When 0 is written in TDRE after reading
TDRE = 1.
When data is written in ICDRT.
When the ninth clock of SCL is rose while the
TDRE flag is 1.
When 0 is written in TEND after reading
TEND = 1.
When data is written in ICDRT.
When a received data is transferred from ICDRS
to ICDRR.
When 0 is written in RDRF after reading
RDRF = 1.
When data is read from ICDRR.
Section 17 I
2
C Bus Interface 2 (IIC2)
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