R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 953

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
16.3.8
SCMR selects Smart Card interface mode and its format.
Note:
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
7
6 to 4
3
2
1
0
*
Bit Name
BCP2
SDIR
SINV
SMIF
Smart Card Mode Register (SCMR)
Can be written to only when TE = RE = 0.
Initial Value
1
All 1
0
0
1
0
R/W
R/W*
R/W*
R/W*
R/W*
Description
Basic Clock Pulse 2
Selects, in combination with the BCP1 and BCP0
bits in SMR, the number of basic clock cycles in a
1-bit transfer interval in Smart Card interface
mode.
For the settings, refer to section 16.3.5, Serial
Mode Register (SMR).
Reserved
These bits are always read as 1.
Serial Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
Serial Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the parity
bit. To invert the parity bit, invert the O/E bit in
SMR.
0: TDR contents are transmitted as they are.
1: TDR contents are inverted before being
Reserved
This bit is always read as 1.
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
1: Smart Card interface mode
Receive data is stored as it is in RDR.
transmitted. Receive data is stored in inverted
form in RDR.
synchronous mode
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
Page 923 of 1448

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