R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 453

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.7
(1)
Except for forcible termination of the DMAC, the operating (including transfer waiting state)
channel setting should not be changed. The operating channel setting should only be changed
when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
• DMAC control starts one cycle before the bus cycle, with output of the internal address.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
φ
DMA Internal
address
DMA register
operation
Consequently, MAR is updated in the bus cycle before DMA transfer. Figure 8.43 shows an
example of the update timing for DMAC registers in dual address transfer mode.
DMA control
DMAC Register Access during Operation
[1] Transfer source address register MAR operation (incremented/decremented/fixed)
[2] Transfer destination address register MAR operation (incremented/decremented/fixed)
[2']Transfer destination address register MAR operation (incremented/decremented/fixed)
[3] Transfer address register MAR restore operation (in block or repeat transfer mode)
Note: In single address transfer mode, the update timing is the same as [1].
Usage Notes
Transfer counter ETCR operation (decremented)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR operation (decremented in block transfer mode)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
Block size counter ETCR restore (in block transfer mode)
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
Idle
[1]
Transfer
source
Read
Figure 8.43 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Write
Section 8 DMA Controller (DMAC)
Transfer
DMA write
[3]
Dead
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DMA
dead
Idle