R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 467

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
9.3.4
EDMDR controls EXDMAC operations.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
15
Bit Name
EDA
EXDMA Mode Control Register (EDMDR)
Initial Value
0
R/W
R/(W)
Description
EXDMA Active
Enables or disables data transfer on the
corresponding channel. When this bit is set to 1, this
indicates that an EXDMA operation is in progress.
When auto request mode is specified (by bits MDS1
and MDS0), transfer processing begins when this
bit is set to 1. With external requests, transfer
processing begins when a transfer request is issued
after this bit has been set to 1. When this bit is
cleared to 0 during an EXDMA operation, transfer is
halted. If this bit is cleared to 0 during an EXDMA
operation in block transfer mode, transfer
processing is continued for the currently executing
one-block transfer, and the bit is cleared on
completion of the currently executing one-block
transfer.
If an external source that ends (aborts) transfer
occurs, this bit is automatically cleared to 0 and
transfer is terminated. Do not change the operating
mode, transfer method, or other parameters while
this bit is set to 1.
0: Data transfer disabled on corresponding channel
[Clearing conditions]
•
•
•
•
1: Data transfer enabled on corresponding channel
Note: The value written in the EDA bit may not be
When the specified number of transfers end
When operation is halted by a repeat area
overflow interrupt
When 0 is written to EDA while EDA = 1
(In block transfer mode, write is effective after
end of one-block transfer)
Reset, NMI interrupt, hardware standby mode
effective immediately.
Section 9 EXDMA Controller (EXDMAC)
Page 437 of 1448