R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 215

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.3.10
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
15
14
13
12
11
Group. The DRAM interface is not supported by the 5-V version.
Bit Name
DRMI
⎯
TPC1
TPC0
SDWCD*
DRAM Access Control Register (DRACCR)
Initial Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM read access cycle
when a continuous external space access cycle
follows a DRAM/synchronous DRAM read access
cycle. Idle cycle insertion conditions, setting of
number of states, etc., comply with settings of bits
ICIS2, ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
Precharge State Control
These bits select the number of states in the RAS
precharge cycle in normal access and refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tcl) inserted
by WTCRB (H) settings during synchronous
DRAM write access (see figure 7.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle
Section 7 Bus Controller (BSC)
Page 185 of 1448