R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1154

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 21 FSI Interface
21.3.4
FSIINS sets an instruction to be sent to the SPI flash memory. When this register has been
modified after the completion of communications setting, the FSI communications operation is
started. The settings of this register should not be modified while the FSI is performing
communications.
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Bit
2 to 0 RBN2
Bit
7 to 0 Bit 7 to Bit 0
Bit Name
RBN1
RBN0
Bit Name
FSI Instruction Register (FSIINS)
Initial
Value
0
0
0
Initial
Value
All 0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Receive Byte Count 2 to 0
These bits specify the number of data bytes to be
received. After the FSI reception operation ends (when
the FSIRXI bit in FSISTR is 1), the RBN value is
decremented (−1) each time FSIRDR is read.
When all the data bytes have been read, the RBN bits
are cleared to B'000.
000: Receives no data
001: Receives one byte of data
010: Receives two bytes of data
011: Receives three bytes of data
100: Receives four bytes of data
101 to 111: Setting prohibited
If reception of five bytes or more is specified, FSIRDR is
overwritten.
Description
These bits store an instruction to be transmitted to the
SPI flash memory.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010