R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1012

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.10
Usage Notes
16.10.1 Module Stop Function Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing the module stop state. For
details, refer to section 26, Power-Down Modes.
16.10.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a
break, even if the FER flag is cleared to 0, it will be set to 1 again.
16.10.3 Mark State and Break Sending
When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and
level are determined by DR and DDR. This can be used to set the TxD pin to mark state or send a
break during serial data transmission. To maintain the communication line at mark state until the
TE bit is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD
pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial
transmission, first set DDR to 1 and clear DR to 0, and then clear the TE bit to 0. When the TE bit
is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD
pin becomes an I/O port, and 0 is output from the TxD pin.
16.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER) is set to 1, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note
also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Page 982 of 1448
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010