R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 509

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
9.4.11
(1)
When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three
cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit
EXDMA cycle and the start of the next transfer.
If there is a transfer request for another channel of higher priority, the transfer request by the
original channel is held pending, and transfer is performed on the higher-priority channel from the
next transfer. Transfer on the original channel is resumed on completion of the higher-priority
channel transfer.
Figures 9.28 to 9.30 show operation timing examples for various conditions.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
φ pin
Bus cycle
CPU
operation
ETEND
EDA bit
Auto Request/Cycle Steal Mode/Normal Transfer Mode
Examples of Operation Timing in Each Mode
Figure 9.28 Auto Request/Cycle Steal Mode/Normal Transfer Mode
EDA = 1
write
0
Bus release
Internal bus space
1
3 cycles
cycles
(No Contention/Dual Address Mode)
EXDMA
read
EXDMA
write
1 cycle
Bus
release
EXDMA
read
EXDMA
write
Section 9 EXDMA Controller (EXDMAC)
Bus
release
EXDMA
Last transfer cycle
read
EXDMA
Page 479 of 1448
write
0