R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 64

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 1 Overview
Page 34 of 1448
Type
Bus
control
Symbol
CS7 to
CS0
AS
AH
RD
HWR
LWR
BREQ-A
BREQ-B
BREQO-A
BREQO-B
BACK-A
BACK-B
UCAS*
LCAS*
3
3
PLQP0144KA-A
38 to 35,
110 to 107
90
90
89
88
87
132
134
130
133
131
135
85
86
H8S/2427, H8S/2427R
PTLG0145JB-A
(in Planning)
M2, N2, M1, L1,
A13, A12, B13,
C12
G10
G10
G12
H11
J13
D5
B5
B6
A6
C7
C6
H12
H10
Pin No.
H8S/2425
PLQ0120LA-A
PLQP0120KA-A I/O
29, 71, 70, 106,
92 to 89
75
75
74
73
72
108
110
106
109
107
111
70
71
Output Signals that select division areas 7
Output When this pin is low, it indicates that
Output Signal for holding the address when
Output When this pin is low, it indicates that
Output Strobe signal indicating that an
Output Strobe signal indicating that an
Input
Output External bus request signal when
Output Indicates the bus is released to the
Output Upper column address strobe signal
Output Lower column address strobe signal
H8S/2427, H8S/2427R, H8S/2425 Group
Function
to 0 in the external address space
address output on the address bus
is valid.
an address/data multiplexed I/O
space is being accessed.
the external address space is being
read.
external address space is to be
written to, and the upper half (D15
to D8) of the data bus is enabled.
Also functions as the write enable
signal for accessing the DRAM
space.
external address space is to be
written to, and the lower half (D7 to
D0) of the data bus is enabled.
The external bus master requests
the bus to this LSI.
the internal bus master accesses an
external space in the external bus
release state.
external bus master.
for accessing the 16-bit DRAM
space. Also functions as the column
address strobe signal for accessing
the 8-bit DRAM space.
for accessing the 16-bit DRAM
space.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010