R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 478

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 9 EXDMA Controller (EXDMAC)
(2)
In single address mode, the EDACK signal is used instead of the source or destination address
register to transfer data directly between an external device and external memory. In this mode,
the EXDMAC accesses the transfer source or transfer destination external device by outputting the
external I/O strobe signal (EDACK), and at the same time accesses the other external device in the
transfer by outputting an address. In this way, EXDMA transfer can be executed in one bus cycle.
In the example of transfer between external memory and an external device with DACK shown in
figure 9.3, data is output to the data bus by the external device and written to external memory in
the same bus cycle.
The transfer direction, that is whether the external device with DACK is the transfer source or
transfer destination, can be specified with the SDIR bit in EDMDR. Transfer is performed from
the external memory (EDSAR) to the external device with DACK when SDIR = 0, and from the
external device with DACK to the external memory (EDDAR) when SDIR = 1.
The setting in the source or destination address register not used in the transfer is ignored.
The EDACK pin becomes valid automatically when single address mode is selected. The EDACK
pin is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in
EDMDR. ETEND is output for one bus cycle.
Page 448 of 1448
Single Address Mode
φ
Address bus
RD
WR
ETEND
Figure 9.2 Example of Timing in Dual Address Mode
read cycle
EXDMA
EDSAR
write cycle
EXDMA
EDDAR
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010