R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 404

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer:
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Section 8 DMA Controller (DMAC)
8.5.3
In common register enabled mode, idle mode can be specified by setting the MDS bit in
DMACRS and the DTIE bit in DMABCRL to 1. In common register disabled mode, idle mode
can be specified by setting the MDS bit in DMACRS and the IDLE bit in DMAECRS to 1.In idle
mode, one byte or word is transferred in response to a single transfer request, and this is executed
the number of times specified in ETCR. One address is specified by MAR, and the other by
IOAR. The transfer direction can be specified by the DTDIR bit in DMACRS. Table 8.5
summarizes register functions in idle mode.
Table 8.5
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented by a data transfer. IOAR specifies the lower 16 bits of the
other address.
Page 374 of 1448
Register
23
23
H'FF
15
Idle Mode
15
Register Functions in Idle Mode
ETCR
MAR
IOAR
0
0
0
DTDIR = 0 DTDIR = 1 Initial Setting
Source
address
register
Destination
address
register
Transfer counter
Function
Destination
address
register
Source
address
register
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Operation
Fixed
Fixed
transfer; transfer
ends when count
reaches H'0000
Jul 22, 2010

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