R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 385

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
13, 12
11
10
Bit Name
DTA5
Initial
Value
All 0
0
0
R/W
R
R/W
R
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Data Transfer Acknowledge 5
These bits enable or disable clearing when DMA
transfer is performed for the internal interrupt
source selected by the DTF3 to DTF0 bits in
DMACRF of channel 5.
It the DTA5 bit is set to 1 when DTE5 = 1, the
internal interrupt source is cleared automatically by
DMA transfer. When DTE5 = 1 and DTA5 = 1, the
internal interrupt source does not issue an interrupt
request to the CPU or DTC.
It the DTA5 bit is cleared to 0 when DTE5 = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an interrupt
request to the CPU or DTC in parallel. In this case,
the interrupt source should be cleared by the CPU
or DTC transfer.
When DTE5 = 0, the internal interrupt source issues
an interrupt request to the CPU or DTC regardless
of the DTA5 bit setting.
The state of the DTME5 bit does not affect the
above operations.
Reserved
This bit is always read as 0 and cannot be modified.
Section 8 DMA Controller (DMAC)
Page 355 of 1448

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