R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 242

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 7 Bus Controller (BSC)
7.5.6
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 7.20 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Page 212 of 1448
Read
(when
RDNn = 0)
Write
Figure 7.20 Example of Timing when Chip Select Assertion Period Is Extended
Extension of Chip Select (CS) Assertion Period
φ
Address bus
CSn
AS
RD
Data bus
HWR, LWR
Data bus
T
h
T
1
Bus cycle
T
Write data
2
H8S/2427, H8S/2427R, H8S/2425 Group
Read data
T
3
REJ09B0565-0100 Rev. 1.00
T
t
Jul 22, 2010