R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 421

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.5.7
In common register enabled mode, block transfer mode can be specified by setting the RSEL4 and
RSEL5 bits in DRSEL corresponding to channels 4 and 5 the BLKE bit in DMACRF to 1. In
common register disabled mode, normal mode can be specified by setting the BLKE bit in
DMACRF to 1. In block transfer mode, a data transfer of the specified block size is carried out in
response to a single transfer request, and this is executed for the number of times specified in
ETCRB. The transfer source is specified by SAR, and the transfer destination by DAR. Either the
transfer source or the transfer destination can be selected as a block area (an area composed of a
number of bytes or words). Table 8.9 summarizes register functions in block transfer mode.
Table 8.9
SAR and DAR specify the start addresses of the transfer source and transfer destination,
respectively, as 24 bits. SAR and DAR can be incremented or decremented by 1 or 2 each time a
byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value
can be set separately for SAR and DAR. Whether a block is to be designated for SAR or for DAR
is specified by the BLKDIR bit in DMABCR in common register enabled mode or the BLKDIR
bit in DMAECRF in common register disabled mode.
To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N
transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL,
and N in ETCRB.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Register
23
23
15
Block Transfer Mode
7
7
ETCRAH
ETCRAL
ETCRB
Register Functions in Block Transfer Mode
SAR
DAR
0
0
0
0
0
Source address
register
Destination
address register
Holds block
size
Block size
counter
Block transfer
counter
Function
Initial Setting
Start address of
transfer source
Start address of
transfer destination
Block size
Block size
Number of block
transfers
Section 8 DMA Controller (DMAC)
Operation
Incremented/decremented
every transfer, or fixed
Incremented/decremented
every transfer, or fixed
Fixed
Decremented every
transfer; ETCRAH value
copied when count
reaches H'00
Decremented every block
transfer; transfer ends
when count reaches
H'0000
Page 391 of 1448