R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 257

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.7
In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing
performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM
space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst
operation is also possible, using fast page mode.
Note: The DRAM interface is not supported by the 5-V version.
7.7.1
Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in DRAMCR. The
relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 7.5.
Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), four areas (areas 2
to 5), and continuous area (areas 2 to 5).
Table 7.5
Note:
With continuous DRAM space, RAS2 is valid. The bus specifications (bus width, number of wait
states, etc.) for continuous DRAM space conform to the settings for area 2.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
RMTS2
0
1
*
DRAM Interface
Setting DRAM Space
Reserved (setting prohibited) in the H8S/2427 Group and H8S/2425 Group.
RMTS1
0
1
0
1
Relation between Settings of Bits RMTS2 to RMTS0 and DRAM Space
RMTS0
1
0
1
0
1
0
1
Area 5
Normal space
Normal space
DRAM space
Continuous synchronous DRAM space*
Mode register settings of synchronous DRAM*
Reserved (setting prohibited)
Continuous
DRAM space
Area 4
Normal space
Normal space
DRAM space
Continuous
DRAM space
Area 3
Normal space
DRAM space
DRAM space
Continuous
DRAM space
Section 7 Bus Controller (BSC)
Area 2
DRAM space
DRAM space
DRAM space
Continuous
DRAM space
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