R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 746

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 11 I/O Ports
11.16
Note: Port H is not supported in the H8S/2425 Group.
Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the
port function control registers, refer to section 11.18, Port Function Control Registers.
• Port H data direction register (PHDDR)
• Port H data register (PHDR)
• Port H register (PORTH)
• Port function control register 0 (PFCR0)
• Port function control register 2 (PFCR2)
• Port H open drain control register (PHODR)
11.16.1 Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H. PHDDR cannot be
read; if it is, an undefined value will be read.
Page 716 of 1448
Bit
7 to 4
3
2
1
0
Bit Name
⎯
PH3DDR
PH2DDR
PH1DDR
PH0DDR
Port H
Initial Value
All 0
0
0
0
0
R/W
⎯
W
W
W
W
Description
Reserved
•
Modes 1, 2, 4, and 3, 5, 7 (EXPE = 1)
Pin PH3 functions as the OE output pin when the
OE output enable bit (OEE) and OE output select
bit (OES) are set to 1. Otherwise, pin PH3
functions as the CS7 output pin when bit PH3DDR
is set to 1 while bit CS7E is 1, and as an input port
when the bit is cleared to 0. When bit CS7E is
cleared to 0, pin PH3 is an I/O port, and its
function can be switched with bit PH3DDR. When
areas 2 to 5 are specified as continuous
SDRAM*
Pin PH2 function as the CS6 output pin when bit
PH2DDR is set to 1 while bit CS6E is 1, and as an
I/O port when the bit is cleared to 0. When bit
CS6E is cleared to 0, pin PH2 is an I/O port, and
its function can be switched with bit PH2DDR.
1
space, OE output is CKE output.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010