R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 182

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 6 Interrupt Controller
6.7
6.7.1
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. However,
if there is an interrupt request of higher priority than that interrupt, interrupt exception handling
will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0. Figure 6.6 shows an example
in which the TCIEV bit in the TPU's TIER_0 register is cleared to 0. The above conflict will not
occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
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Internal
address bus
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
φ
Usage Notes
Conflict between Interrupt Generation and Disabling
Figure 6.6 Conflict between Interrupt Generation and Disabling
TIER_0 write cycle by CPU
TIER_0 address
TCIV exception handling
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010