R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 229

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
(2)
Figure 7.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access
space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The
amount of data that can be accessed at one time is one byte or one word, and a longword access is
executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
16-Bit Access Space
Figure 7.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
Figure 7.8 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
Byte size
Byte size
Word size
Longword
size
• Even address
• Odd address
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
1st bus cycle
2nd bus cycle
D15
D15
Upper data bus
Upper data bus
D8 D7
D8 D7
Lower data bus
Lower data bus
Section 7 Bus Controller (BSC)
D0
D0
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