R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 351

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
R4F24278NVFQU
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Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
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H8S/2427, H8S/2427R, H8S/2425 Group
7.15.4
(1)
Be sure to set the clock to be connected to the synchronous DRAM to SDRAMφ.
(2)
In the continuous synchronous DRAM space, insertion of the wait state by the WAIT pin is
disabled regardless of the setting of the WAITE bit in BCR.
(3)
This LSI cannot carry out the bank control of the synchronous DRAM. All banks are selected.
(4)
The burst read/burst write mode of the synchronous DRAM is not supported. When setting the
mode register of the synchronous DRAM, set to the burst read/single write and set the burst length
to 1.
(5)
When connecting a synchronous DRAM having CAS latency of 1, set the BE bit to 0 in the
DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2427 Group and H8S/2425
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Connection Clock
WAIT Pin
Bank Control
Burst Access
CAS Latency
Group.
Notes on Usage of the Synchronous DRAM
Section 7 Bus Controller (BSC)
Page 321 of 1448

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