R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1052

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 17 I
17.4.6
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
17.4.7
Flowcharts in respective modes that use the I
Page 1022 of 1448
SCL or SDA
input signal
Sampling
clock
Noise Canceler
Example of Use
2
C Bus Interface 2 (IIC2)
Figure 17.13 Block Diagram of Noise Canceler
Sampling clock
D
System clock
period
Latch
C
Q
D
2
C bus interface are shown in figures 17.14 to 17.17.
Latch
C
Q
Match detector
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
SCL or SDA
Internal
signal
Jul 22, 2010