R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1013

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
16.10.5 Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
16.10.6 Restrictions on Use of DMAC or DTC
1. When an external clock source is used as the serial clock, the transmit clock should not be
2. When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
input until at least 5 φ clock cycles after TDR is updated by the DMAC or DTC. Incorrect
operation may occur if the transmit clock is input within 4 φ clock cycles after TDR is updated.
(Figure 16.35)
SCI receive-data-full interrupt (RXI).
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
Figure 16.35 Example of Clocked Synchronous Transmission Using DTC
t
LSB
D0
D1
D2
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
D3
D4
D5
D6
D7
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