R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 997

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
16.7.6
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 16.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sampled from the receiving end after transmission of one frame is
2. The TEND bit in SSR is not set for a frame for which an error signal is received. The contents
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
4. Transmission of one frame, including a retransfer, is judged to have been completed, and the
Figure 16.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC or DMAC to be activated with a TXI interrupt
source. In a transmit operation, a TXI interrupt request will be generated if the TIE bit in SCR is 1
when the TEND flag in SSR is set to 1. If the TXI interrupt request is designated beforehand as a
DTC or DMAC activation source, the DTC or DMAC will be activated by the TXI interrupt
request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are
automatically cleared to 0 when data transfer is performed by the DTC or DMAC. In the event of
an error, the SCI retransmits the same data automatically. During this period, the TEND flag
remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and DTC or
DMAC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI interrupt request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or
DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures,
refer to section 10, Data Transfer Controller (DTC), or section 8, DMA Controller (DMAC).
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next parity
bit is sampled.
of TSR are retransmitted automatically.
TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transfers the next transmit data.
Data Transmission (Except for Block Transfer Mode)
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
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