R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 751

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
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Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2427, H8S/2427R, H8S/2425 Group
• PH2/CS6/IRQ6-B
Note:
• PH1/CS5/RAS5*
Notes: 1. Not supported in the H8S/2427 Group.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Operating
mode
EXPE
CS6E
PH2DDR
Pin
function
SDPSTP
Operating
mode
EXPE
RMTS2 to
RMTS0
CS5E
PH1DDR
Pin
function
The pin function is switched as shown below according to the combination of the operating
mode, bit CS6E in PFCR0, and bit PH2DDR.
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in
SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR.
*
2. Not supported in the 5-V version.
input
PH1
Area 5 is normal space
0
IRQ6-B input when the ITS6 bit in ITSR is 1.
0
input
PH2
output
PH1
0
1
input
PH1
0
2
0
/SDRAMφ*
output
PH2
1
output
1
1, 2, 4
CS5
1
1, 2, 4
input
PH1
Area 5 is DRAM
0
input
PH2
1
0
0
output
space
PH1
1
1
output
RAS5*
CS6
output
1
1
IRQ6-B interrupt input*
input
PH1
0
input
PH2
1
0
0
output
PH1
1
0
input
PH1
Area 5 is normal space
output
0
PH2
1
0
output
PH1
1
3, 5, 7
input
PH1
input
PH2
0
0
3, 5, 7
1
output
CS5
1
0
1
output
PH2
input
PH1
1
Area 5 is DRAM
0
0
1
output
space
PH1
Section 11 I/O Ports
1
input
PH2
Page 721 of 1448
0
RAS5*
output
1
1
output
SDRAMφ
CS6
output*
1
0

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