R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 976

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
H8S/2427, H8S/2427R, H8S/2425 Group
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component cycles:
an ID transmission cycle which specifies the receiving station, and a data transmission cycle to the
specified receiving station. The multiprocessor bit is used to differentiate between the ID
transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID
transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure
16.10 shows an example of inter-processor communication using the multiprocessor format. The
transmitting station first sends communication data with a 1 multiprocessor bit added to the ID
code of the receiving station. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR flags, RDRF,
FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception
of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit
is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this
time, an RXI interrupt is generated. When the MPIE bit is cleared to 0, the receive operation is
performed regardless of the value of the multiprocessor bit. The multiprocessor bit is stored in the
MPB bit in SSR.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Page 946 of 1448
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010

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