R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 345

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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H8S/2427, H8S/2427R, H8S/2425 Group
7.12.3
Figure 7.96 shows the timing for transition to the bus released state.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
HWR, LWR
Address bus
Data bus
BREQO
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Note: The refresh control function is not supported by the 5-V version.
BREQ
BACK
RD
AS
Low level of BREQ signal is sampled at the rising edge of φ.
Bus control signal returns high at end of external space access cycle.
At least two states from sampling of BREQ signal.
BACK signal is driven low, releasing bus to an external bus master.
BREQ signal state is sampled even in external bus released state.
High level of BREQ signal is sampled.
BACK signal is driven high, completing the external bus release cycle.
When there is an external access or a refresh request from an internal bus master
in external bus released state while the BREQOE bit is set to 1, BREQO signal goes low.
Normally BREQO signal goes high 1.5 states after rising edge of BACK signal. If BREQO
signal is asserted because of CBR-refreshing request, it retains low until CBR-refresh cycle starts up.
φ
Transition Timing
[1]
T
External
access cycle
1
Figure 7.96 Bus Released State Transition Timing
T
2
[2]
[3]
[4]
[7]
High impedance
High impedance
High impedance
High impedance
High impedance
External bus released state
[5]
Section 7 Bus Controller (BSC)
[6]
Page 315 of 1448
[8]
CPU cycle

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