R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 459

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Section 8 DMA Controller (DMAC)
(8)
Channel Re-Setting
To reactivate a number of channels when multiple channels are enabled, use exclusive handling of
transfer end interrupts, and perform exclusive control of DMABCR control bits in common
register enabled mode, or DMAECRS or DMAECRF control bits in common register disabled
mode.
Note, in particular, that in cases where multiple interrupts are generated between reading and
writing of DMABCR in common register enabled mode or DMAECRS or DMAECRF in common
register disabled mode, and a DMABCR operation in common register enabled mode or
DMAECRS or DMAECRF operation in common register disabled mode is performed during new
interrupt handling, the DMABCR write data in common register enabled mode or DMAECRS or
DMAECRF write data in common register disabled mode in the original interrupt handling routine
will be incorrect, and the write may invalidate the results of the operations by the multiple
interrupts. Ensure that overlapping DMABCR operations in common register enabled mode or
DMAECRS or DMAECRF operations in common register disabled mode are not performed by
multiple interrupts, and use of a bit-manipulation instruction to prevent separation between read
and write operations.
Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must
first be read while cleared to 0 before the CPU can write 1 to them.
REJ09B0565-0100 Rev. 1.00
Page 429 of 1448
Jul 22, 2010