R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 398

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 8 DMA Controller (DMAC)
8.5
8.5.1
Table 8.3 lists the DMAC transfer modes.
Table 8.3
Page 368 of 1448
Channels 0,
1, 2, and 3:
Short
address
mode
Operation
Transfer Modes
DMAC Transfer Modes
Dual Address Mode
1-byte or 1-word transfer for a single
transfer request.
Specify source and destination
addresses to transfer data in two bus
cycles.
(1) Sequential mode
(2) Idle mode
(3) Repeat mode
Single Address Mode
1-byte or 1-word transfer for a single
transfer request.
1-bus cycle transfer by means of
DACK pin instead of using address for
specifying I/O.
Sequential mode, idle mode, or repeat
mode can be specified.
Memory address incremented or
decremented by 1 or 2.
Number of transfers: 1 to 65,536
Memory address fixed.
Number of transfers: 1 to 65,536
Memory address incremented or
decremented by 1 or 2.
Continues transfer after sending
number of transfers (1 to 256) and
restoring the initial value.
Transfer Mode
Transfer Source
TPU channel 0 to 5
compare match/input
capture A interrupt
SCI transmit data
empty interrupt
SCI receive data full
interrupt
A/D converter
conversion end
interrupt
External request
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Remarks
Up to 4 channels
can operate
independently.
Common register
enabled mode:
Single address
mode applies to
only channels 1
and 3.
Common register
disabled mode:
Single address
mode applies to
only channels 0
and 1.
Jul 22, 2010