R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 952

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R4F24278NVFQU

Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet

Specifications of R4F24278NVFQU

Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer:
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Section 16 Serial Communication Interface (SCI, IrDA, CRC)
Note:
Page 922 of 1448
Bit
2
1
0
Bit Name
TEND
MPB
MPBT
*
Only 0 can be written, to clear the flag.
1
0
0
Initial Value
R/W
R
R
R/W
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
[Clearing conditions]
This bit is not used in Smart Card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Description
Transmit End
Multiprocessor Bit
When the TE bit in SCR is 0
If the ERS bit is 0 and the TDRE bit is 1 after the
specified interval after transmission of 1-byte
data
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 12.5 etu after transmission
GM = 0, BLK = 1: 11.5 etu after transmission
GM = 1, BLK = 0: 11.0 etu after transmission
GM = 1, BLK = 1: 11.0 etu after transmission
When 0 is written to TEND after reading TEND
= 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010

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