R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 492
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R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 9 EXDMA Controller (EXDMAC)
When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the EXDMA
transfer period. In block transfer mode, since a block-size transfer is carried out without
interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current
block-size transfer.
In burst mode, transfer is halted for up to three EXDMA transfers following the bus cycle in
which 0 is written to the EDA bit. The EDA bit remains set to 1 from the time of the 0-write until
the end of the last EXDMA cycle.
Writes (except to the EDA bit) are prohibited to registers of a channel for which the EDA bit is set
to 1. When changing register settings after a 0-write to the EDA bit, it is necessary to confirm that
the EDA bit has been cleared to 0.
Figure 9.12 shows the procedure for changing register settings in an operating channel.
Page 462 of 1448
Changing register settings
Figure 9.12 Procedure for Changing Register Settings in Operating Channel
Change register settings
changes completed
in operating channel
Write 0 to EDA bit
Register setting
Read EDA bit
EDA bit = 0?
Yes
No
[1]
[2]
[3]
[4]
[1] Write 0 to the EDA bit in EDMDR.
[2] Read the EDA bit.
[3] Confirm that EDA = 0. If EDA = 1, this
[4] Write the required set values to the
indicates that EXDMA transfer is in
progress.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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