R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 24

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.8 IrDA Operation .................................................................................................................. 974
16.9 Interrupt Sources................................................................................................................ 978
16.10 Usage Notes ....................................................................................................................... 982
16.11 CRC Operation Circuit ...................................................................................................... 988
Section 17 I
17.1 Features.............................................................................................................................. 995
17.2 Input/Output Pins............................................................................................................... 997
17.3 Register Descriptions ......................................................................................................... 998
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16.7.2 Data Format (Except for Block Transfer Mode)................................................... 962
16.7.3 Block Transfer Mode ............................................................................................ 963
16.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 964
16.7.5 Initialization.......................................................................................................... 966
16.7.6 Data Transmission (Except for Block Transfer Mode)......................................... 967
16.7.7 Serial Data Reception (Except for Block Transfer Mode).................................... 970
16.7.8 Clock Output Control............................................................................................ 972
16.9.1 SCI Normal Mode................................................................................................. 978
16.9.2 Smart Card Interface Mode................................................................................... 980
16.10.1 Module Stop Function Setting .............................................................................. 982
16.10.2 Break Detection and Processing ........................................................................... 982
16.10.3 Mark State and Break Sending ............................................................................. 982
16.10.4 Receive Error Flags and Transmit Operations
16.10.5 Relation between Writes to TDR and the TDRE Flag .......................................... 983
16.10.6 Restrictions on Use of DMAC or DTC................................................................. 983
16.10.7 Operation in Case of Mode Transition.................................................................. 984
16.10.8 External Clock Input in Clocked Synchronous Mode........................................... 987
16.11.1 Features................................................................................................................. 988
16.11.2 Register Descriptions............................................................................................ 989
16.11.3 CRC Operation Circuit Operation ........................................................................ 991
16.11.4 Note on CRC Operation Circuit............................................................................ 994
17.3.1 I
17.3.2 I
17.3.3 I
17.3.4 I
17.3.5 I
17.3.6 Slave Address Register (SAR)............................................................................ 1009
17.3.7 I
17.3.8 I
17.3.9 I
(Clocked Synchronous Mode Only) ..................................................................... 982
2
2
2
2
2
2
2
2
2
C Bus Control Register A (ICCRA) ................................................................. 1000
C Bus Control Register B (ICCRB) ................................................................. 1002
C Bus Mode Register (ICMR).......................................................................... 1003
C Bus Interrupt Enable Register (ICIER)......................................................... 1005
C Bus Status Register (ICSR)........................................................................... 1007
C Bus Transmit Data Register (ICDRT) .......................................................... 1010
C Bus Receive Data Register (ICDRR)............................................................ 1010
C Bus Shift Register (ICDRS).......................................................................... 1010
C Bus Interface 2 (IIC2)................................................................ 995