R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 1137

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
20.4.7
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Figure 20.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Figure 20.12 Example of Initial Settings in Clock Synchronous Communication Mode
Initial Settings in Clock Synchronous Communication Mode
[1]
[2]
[3]
[4]
[5]
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Clock Synchronous Communication Mode
Specify TE, RE, TEIE, TIE, RIE, and
Specify SDOS, SSCKOS, SCSOS,
Specify MSS and SCKS in SSCRH
Clear TE and RE bits in SSER to 0
Specify CPOS, CKS2, CKS1, and
CEIE bits in SSER simultaneously
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
TENDSTS, SCSATS, and
Start setting initial values
SSODTS bits in SSCR2
Clear a bit in DDR to 0
CKS0 bits in SSMR
End
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
[3] Selects clock synchronous communication mode and
[4] Specify clock polarity selection and transfer clock rate
[5] Enables/disables interrupt request to the CPU.
selection.
specify transmit/receive data length.
selection.
Section 20 Synchronous Serial Communication Unit (SSU)
Page 1107 of 1448