R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 402
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R4F24278NVFQU
Manufacturer Part Number
R4F24278NVFQU
Description
MCU 512K/48K 2.7-5.5V 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2400r
Datasheet
1.R4F24278NVFQU.pdf
(1482 pages)
Specifications of R4F24278NVFQU
Core Processor
H8S/2600
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
98
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
REALTEK
Quantity:
2 300
Company:
Part Number:
R4F24278NVFQU
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 DMA Controller (DMAC)
Figures 8.3 and 8.4 show an example of the setting procedure for sequential mode in common
register enabled mode and common register disabled mode, respectively.
Page 372 of 1448
Sequential mode setting
and transfer destination
Set number of transfers
Set transfer source
Read DMABCRL
Sequential mode
Set MDLCFGCR
Set DMABCRH
Set DMABCRL
Set DMACRS
Set DRSEL
addresses
Figure 8.3 Example of Sequential Mode Setting Procedure
(Common Register Enabled Mode)
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Set the DMCOMMD bit in MDLCFGCR to 1.
[2] Set RSEL3, RSEL2, RSEL1, or RSEL0 bit in DRSEL to 1
[3] Set each bit in DMABCRH.
[4] Set the transfer source address and transfer destination
[5] Set the number of transfers in ETCR.
[6] Set each bit in DMACRS.
[7] Read the DTE bit in DMABCRL as 0.
[8] Set each bit in DMABCRL.
depending on the channel to be set. Here, set RSEL5 to 0
when channel 3 or 2 is to be set and set RSEL4 to 0 when
channel 1 or 0 is to be set.
address in MAR and IOAR.
•
•
• Specify enabling or disabling of internal interrupt
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the MDS bit to 0 to select sequential mode.
• Specify the transfer direction with the DTDIR bit.
• Select the activation source with bits DTF3 to DTF0.
clearing with the DTA bit.
decremented with the DTID bit.
interrupts with the DTIE bit.
Specify enabling or disabling of transfer end
Set the DTE bit to 1 to enable transfer.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
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