R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 537

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
5
4
Bit Name
SWDTIF
RRS
Initial Value
0
0
R/W
R/W
R/W
DTC Software Activation Interrupt Flag
Description
Indicates whether an interrupt request has been
sent to the CPU. When a chain transfer is to be
continuously performed (CHNE = 1), this bit will
not be set to 1.
Only 0 can be written to this bit after this bit has
been read as 1.
0: No interrupt request
1: Interrupt request is generated
[Clearing conditions]
•
•
[Setting conditions]
•
•
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer
information read. A DTC vector number is always
compared with the vector number for the previous
activation. If the vector numbers match and this bit
is set to 1, the DTC data transfer is started without
reading a vector address and transfer information.
If the previous DTC activation is a chain transfer,
the vector address read and transfer information
read are always performed.
0: Transfer information read skip is not performed.
1: Transfer information read skip is performed
when the vector numbers match.
When 0 is written to this bit after this bit is read
as 1
When the SWDTE bit is set to 1
When the specified number of data transfers
have ended
When the DISEL bit is 1 and one data transfer
has ended
Section 10 Data Transfer Controller (DTC)
Page 507 of 1448