R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 373

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
8.3.10
DMACRF controls the operation of DMAC channels 4 and 5.
• DMACRF4 and DMACRF5
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
15
14
13
12
11
Bit Name
DTSZ
SAID
SAIDE
BLKDIR
BLKE
DMA Control Register F (DMACRF)
0
0
0
0
0
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
Description
Data Transfer Size
Selects the size of data to be transferred at one
time.
0: Byte-size transfer
1: Word-size transfer
Source Address Increment/Decrement
Source Address Increment/Decrement Enable
These bits specify whether the source address
register (SAR) is to be incremented, decremented,
or left unchanged, when data transfer is
performed.
00: SAR is fixed
01: SAR is incremented after a data transfer
10: SAR is fixed
11: SAR is decremented after a data transfer
Block Direction
Block Enable
The BLKE bit specifies whether normal mode or
block transfer mode is to be used for data transfer.
If block transfer mode is specified, the BLKDIR bit
specifies whether the source side or the
destination side is to be the block area.
x0: Transfer in normal mode
01: Transfer in block transfer mode (destination
11: Transfer in block transfer mode (source side is
When DTSZ = 0, SAR is incremented by 1
When DTSZ = 1, SAR is incremented by 2
When DTSZ = 0, SAR is decremented by 1
When DTSZ = 1, SAR is decremented by 2
side is block area)
block area)
Section 8 DMA Controller (DMAC)
Page 343 of 1448