R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 391

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Bit
2
1
0
Bit Name
DTIE5
DMIE4
DTIE4
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
Description
Data Transfer End Interrupt Enable 5
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 5 ends. If the DTE5 bit is
cleared to 1 when DTIE5 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE5 bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the transfer counter and address
register again, and then setting the DTE5 bit to 1.
Data Transfer Interrupt Enable 4
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 4 has been interrupted. If
the DTME4 bit is cleared to 0 when DMIE4 = 1, the
DMAC regards this as indicating the break in a
transfer, and issues a transfer break interrupt
request to the CPU or DTC.
A transfer break interrupt can be canceled either by
clearing the DMIE4 bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the DTME4 bit to 1.
Data Transfer End Interrupt Enable 4
Enables or disables an interrupt to the CPU or DTC
when transfer on channel 4 ends. If the DTE4 bit is
cleared to 0 when DTIE4 = 1, the DMAC regards
this as indicating the end of a transfer, and issues a
transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by
clearing the DTIE4 bit to 0 in the interrupt handling
routine, or by performing processing to continue
transfer by setting the transfer counter and address
register again, and then setting the DTE4 bit to 1.
Section 8 DMA Controller (DMAC)
Page 361 of 1448