R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 14

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.12 Bus Release........................................................................................................................ 313
7.13 Bus Arbitration .................................................................................................................. 317
7.14 Bus Controller Operation in Reset ..................................................................................... 319
7.15 Usage Notes ....................................................................................................................... 320
Section 8 DMA Controller (DMAC)................................................................. 323
8.1
8.2
8.3
8.4
Page xiv of xxx
7.12.1 Operation .............................................................................................................. 313
7.12.2 Pin States in External Bus Released State ............................................................ 314
7.12.3 Transition Timing ................................................................................................. 315
7.13.1 Operation .............................................................................................................. 317
7.13.2 Bus Transfer Timing............................................................................................. 318
7.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 320
7.15.2 External Bus Release Function and Software Standby ......................................... 320
7.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 320
7.15.4 Notes on Usage of the Synchronous DRAM ........................................................ 321
Features.............................................................................................................................. 323
Channel Specifications....................................................................................................... 325
8.2.1
8.2.2
8.2.3
Register Descriptions ......................................................................................................... 329
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10 DMA Control Register F (DMACRF) .................................................................. 343
8.3.11 DMA Enable Control Register F (DMAECRF).................................................... 346
8.3.12 DMA Register Select Register (DRSEL).............................................................. 349
8.3.13 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 351
8.3.14 DMA Terminal Control Register (DMATCR) ..................................................... 362
8.3.15 Module Configuration Register (MDLCFGCR)................................................... 363
Activation Sources............................................................................................................. 364
8.4.1
8.4.2
8.4.3
Channel Switching................................................................................................ 325
Input/Output Pins.................................................................................................. 326
Interrupt Vectors................................................................................................... 328
Memory Address Register (MAR)........................................................................ 332
I/O Address Register (IOAR) ............................................................................... 332
Transfer Count Register (ETCR) .......................................................................... 333
DMA Control Register S (DMACRS) .................................................................. 333
DMA Enable Control Register S (DMAECRS).................................................... 337
DMA Register Control Register (DMARCR) ...................................................... 340
Source Address Register (SAR)............................................................................ 341
Destination Address Register (DAR).................................................................... 341
Transfer Count Registers A and B (ETCRA and ETCRB)................................... 342
Activation by Internal Interrupt Request .............................................................. 366
Activation by External Request ............................................................................ 367
Activation by Auto-Request ................................................................................. 367