R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 265

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
7.7.8
When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one T
always inserted when DRAM space is accessed. From one to four T
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T
DRAM connected and the operating frequency of this LSI. Figure 7.37 shows the timing when
two T
cycles.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Read
Write
Note: n = 2 to 5
p
states are inserted. The setting of bits TPC1 and TPC0 is also valid for T
Precharge State Control
φ
Address bus
RASn (CSn)
UCAS, LCAS
WE (HWR)
OE (RD)
Data bus
WE (HWR)
OE (RD)
Data bus
Figure 7.37 Example of Timing with Two-State Precharge Cycle
T
p1
(RAST = 0, CAST = 0)
Row address
T
p2
High
High
T
r
p
states can be selected by
T
c1
Column address
p
cycles according to the
Section 7 Bus Controller (BSC)
p
states in refresh
T
c2
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p
state is