R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 942

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 16 Serial Communication Interface (SCI, IrDA, CRC)
16.3.6
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
16.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication
interface mode and Smart Card interface mode.
• Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Page 912 of 1448
Bit
7
6
5
Bit Name
TIE
RIE
TE
Serial Control Register (SCR)
0
0
0
Initial Value
R/W
R/W
R/W
R/W*
1
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
TXI interrupt request cancellation can be
performed by reading 1 from the TDRE flag, then
clearing it to 0, or clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
RXI and ERI interrupt request cancellation can be
performed by reading 1 from the RDRF flag, or the
FER, PER, or ORER flag, then clearing the flag to
0, or by clearing the RIE bit to 0.
Transmit Enable
When this bit s set to 1, transmission is enabled. In
this state, serial transmission is started when
transmit data is written to TDR and the TDRE flag
in SSR is cleared to 0. SMR setting must be
performed to decide the transfer format before
setting the TE bit to 1.
The TDRE flag in SSR is fixed at 1 if transmission
is disabled by clearing this bit to 0.
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010