R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 987

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
16.6.4
Figure 16.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF flags to 0 before resuming reception. Figure 16.19 shows a sample
flowchart for serial data reception.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Serial
clock
Serial
data
RDRF
ORER
or output, starts receiving data, and stores the received data in RSR.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
RXI interrupt request
generated
Serial Data Reception (Clocked Synchronous Mode)
Figure 16.18 Example of SCI Operation in Reception
Bit 7
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
Bit 0
1 frame
Bit 7
Section 16 Serial Communication Interface (SCI, IrDA, CRC)
Bit 0
RXI interrupt request
generated
Bit 1
ERI interrupt request
generated by overrun
error
Bit 6
Page 957 of 1448
Bit 7