R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 415

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

H8S/2427, H8S/2427R, H8S/2425 Group
Figures 8.12 and 8.13 show an example of the setting procedure for single address mode (when
sequential mode is specified) in common register enabled mode and common register disabled
mode, respectively.
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010
Set transfer source and
Set number of transfers
(when Sequential Mode is Specified) (Common Register Enabled Mode)
Single address mode
transfer destination
Read DMABCRL
Set MDLCFGCR
Set DMABCRH
Single address
Set DMABCRL
Figure 8.12 Example of Single Address Mode Setting Procedure
Set DMACRS
mode setting
Set DRSEL
addresses
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Set the DMCOMMD bit in MDLCFGCR to 1.
[2] Set RSEL3 or RSEL1 bit in DRSEL to 1 depending on the
[3] Set each bit in DMABCRH.
[4] Set the transfer source address and transfer destination
[5] Set the number of transfers in ETCR.
[6] Set each bit in DMACRS.
[7] Read the DTE bit in DMABCRL as 0.
[8] Set each bit in DMABCRL.
channel to be set. Here, set RSEL5 to 0 when channel 3 is
to be set and set RSEL4 to 0 when channel 1 is to be set.
address in MAR and IOAR.
•
•
• Set the SAE bit to 1 to select single address mode.
• Specify enabling or disabling of internal interrupt
• Set the transfer data size with the DTSZ bit.
• Specify whether MAR is to be incremented or
• Clear the MDS bit to 0 to select sequential mode.
• Specify the transfer direction with the DTDIR bit.
• Select the activation source with bits DTF3 to DTF0.
clearing with the DTA bit.
decremented with the DTID bit.
with DTIE bit.
Specify enabling or disabling of transfer end interrupts
Set the DTE bit to 1 to enable transfer.
Section 8 DMA Controller (DMAC)
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