R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 15

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.5
8.6
8.7
Section 9 EXDMA Controller (EXDMAC) ......................................................431
9.1
9.2
9.3
9.4
Operation ........................................................................................................................... 368
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 407
8.5.11 Write Data Buffer Function .................................................................................. 413
8.5.12 Multi-Channel Operation...................................................................................... 416
8.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles,
8.5.14 DMAC and NMI Interrupts .................................................................................. 419
8.5.15 Forcible Termination of DMAC Operation .......................................................... 420
Interrupt Sources................................................................................................................ 421
Usage Notes ....................................................................................................................... 423
Features.............................................................................................................................. 431
Input/Output Pins............................................................................................................... 433
Register Descriptions ......................................................................................................... 434
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
Operation ........................................................................................................................... 446
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 473
Transfer Modes..................................................................................................... 368
Sequential Mode ................................................................................................... 370
Idle Mode.............................................................................................................. 374
Repeat Mode......................................................................................................... 378
Single Address Mode............................................................................................ 383
Normal Mode........................................................................................................ 387
Block Transfer Mode ............................................................................................ 391
Basic Bus Cycles .................................................................................................. 397
DMA Transfer (Dual Address Mode) Bus Cycles................................................ 398
and EXDMAC ...................................................................................................... 418
EXDMA Source Address Register (EDSAR)....................................................... 434
EXDMA Destination Address Register (EDDAR)............................................... 435
EXDMA Transfer Count Register (EDTCR)........................................................ 435
EXDMA Mode Control Register (EDMDR) ........................................................ 437
EXDMA Address Control Register (EDACR) ..................................................... 442
Transfer Modes..................................................................................................... 446
Address Modes ..................................................................................................... 447
EXDMA Transfer Requests.................................................................................. 451
Bus Modes ............................................................................................................ 452
Transfer Modes..................................................................................................... 454
Repeat Area Function ........................................................................................... 456
Registers during EXDMA Transfer Operation ..................................................... 459
Channel Priority Order.......................................................................................... 463
EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 466
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