R4F24278NVFQU Renesas Electronics America, R4F24278NVFQU Datasheet - Page 130

• Manufacturer Part Number: R4F24278NVFQU
• Description: MCU 512K/48K 2.7-5.5V 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2400r

Specifications of R4F24278NVFQU

• Core Processor: H8S/2600
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, Smart Card, SPI, SSU, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 4 Resets
4.3.1
TCSR selects the clock source to be input to TCNT of the watchdog timer, and the timer mode.
For details on the watchdog timer reset, see section 15, Watchdog Timer (WDT).
4.3.2
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows. For details on the watchdog timer
reset, see section 15, Watchdog Timer (WDT).
4.4
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI by pin reset, the RES pin should be held low at least for
10 ms at a power-on. When a reset is input during operation, the RES pin should be held low at
least for 2 ms. Resetting the LSI initializes the internal state of the CPU and the registers of the
on-chip peripheral modules.
4.5
This is an internal reset generated by the watchdog timer.
When the RSTE bit in RSTCSR is set to 1, if the TCNT overflows, a watchdog timer reset is
issued for 518 system clocks.
For details on the watchdog timer reset, see section 15, Watchdog Timer (WDT).
4.6
Reading RSTCSR determines which reset generation source was used to execute the reset
exception handling. Figure 4.2 shows an example of the flow to identify a reset generation source.
Page 100 of 1448
Timer Control/Status Register (TCSR)
Reset Control/Status Register (RSTCSR)
Pin Reset
Watchdog Timer Reset
Determination of Reset Generation Source
H8S/2427, H8S/2427R, H8S/2425 Group
REJ09B0565-0100 Rev. 1.00
Jul 22, 2010